Along with high integration, high performance, and low power consumption in semiconductor devices, a low-resistance gate material is required to reduce a gate length in transistors and memory cells through formation of fine patterns and to improve device characteristics. The thickness of a gate insulation layer gradually decreases to increase a channel current in a transistor and a memory cell due to low power consumption. In order to prevent short channel effects caused by the reduction of the gate length in a transistor and secure a margin against punchthrough, the sacrificial resistance, for example, sheet resistance and contact resistance of a source/drain region, should be reduced while a source/drain junction is formed to be shallow.
Therefore, research has been conducted on a salicide (self-aligned silicide) process in which a silicide is formed on the surfaces of a gate and a source/drain region to thereby reduce the resistivity of the gate and the sheet resistance and contact resistance of the source/drain region. The salicide process indicates selective formation of a silicide region only on a gate and a source/drain region.
The silicide region is formed of titanium silicide (TiSi.sub.2) or materials of the group-VIII suicides (e.g., PtSi.sub.2, PdSi.sub.2, CoSi.sub.2, and NiSi.sub.2).
Meanwhile, a capacitor is formed after a salicide process in an MDL (Merged DRAM Logic) device having a memory device and a logic device on the same chip. Heat treatment for forming the capacitor results in agglomeration of silicide, increasing the contact resistance and sheet resistance of a source/drain region and degrading junction leakage characteristics due to diffusion of metal atoms.
Accordingly, titanium silicide and cobalt silicide are widely used due to their high temperature stability and low resistivity. Of the two the latter is more popular than the former because it is less dependent on the critical dimension of a gate in a semiconductor devices having a 0.25 .mu.m design rule. Cobalt silicide offers the benefits of low resistivity (16-18 .mu..OMEGA.cm) and high temperature stability (at about 900.degree. C.).
A cobalt salicide process has a distinctive shortcoming in that silicide overgrows on a gate sidewall spacer used to form a silicide region in self-alignment or cobalt is oxidized. In order to prevent oxidization of cobalt and achieve a good quality silicide, there is disclosed in U.S. Pat. No. 5,567,651 a method of forming a capping layer by depositing a conductor such as titanium nitride (TiN) or titanium tungsten (TiW) on a cobalt layer.
FIG. 1 is a flowchart of a cobalt salicide process described in the above U.S. patent. Referring to FIG. 1, a cobalt layer is deposited after wet cleaning for removing a native oxide layer on silicon and polysilicon surfaces. Then, a capping layer is formed by depositing, for example, titanium nitride on the cobalt layer in-situ. Cobalt monosilicide (CoSi) is formed by a primary heat treatment and then unreacted cobalt and titanium nitride layers are removed by wet etching. Subsequently, the cobalt monosilicide is phase-transited to cobalt disilicide (CoSi.sub.2) having low resistivity by a secondary heat treatment.
FIGS. 2 and 3 are sectional views sequentially illustrating a MOS (Meta-Oxide-Semiconductor) transistor fabrication method to which the conventional salicide process is applied. Referring to FIG. 2, a field region and an active region are defined on a silicon substrate 10 by forming a field oxide film 12 on the substrate 10 by a general device isolation technique. After a gate insulation layer 14 and a polysilicon gate layer 16 for a transistor are sequentially formed on the active region, sidewall spacers 18 are formed at edges of the polysilicon gate layer 16 by depositing an insulation layer on the resultant structure and anisotropically etching the insulation layer. Subsequently, a source/drain region 20 is formed by ion implanting an N-type impurity for an N-channel transistor and a P-type impurity for a P-channel transistor. After cobalt 22 is deposited on the resultant structure by sputtering, a capping layer 24 is formed by in-situ depositing titanium nitride on the cobalt layer 22 by sputtering.
Referring to FIG. 3, the substrate 10 is subject to a primary heat treatment at 400-600.degree. C. in a general rapid thermal annealer, causing a silicide reaction where cobalt is in contact with silicon. Thus, cobalt monosilicide regions 26 and 28 are formed on the source/drain region 20 and the polysilicon gate layer 16, without silicide on the field region and the sidewall spacers 8. Subsequently, unreacted cobalt and capping layers are selectively removed by wet etching using an etchant which does not attack the cobalt monosilicide regions 26 and 28, the silicon substrate 10, and the gate insulation layer 14. Then, the cobalt monosilicide regions 26 and 28 are phase-transited to cobalt disilicide having low resistivity by a secondary heat treatment at 700-900.degree. C. in the general rapid thermal annealer.
In the conventional method as described above, stresses are concentrated due to a rapid silicide reaction by the second heat treatment at high temperature or the morphology of the cobalt disilicide regions is poor as shown in an SEM (Scanning Electron Microscope) picture of FIG. 4, thereby producing a rough silicide-silicon interface. In addition, the silicide reaction entails diffusion of cobalt and silicon. The cobalt diffusion in the secondary heat treatment causes silicide spiking even in the vicinity of a depletion layer of a source/drain junction, increasing a junction leakage current.